Despite Samsung Electronics’ plans to mass-produce a 3-nanometer semiconductor foundry CPU this year, poor yield and delays in mass production are projected to limit its use to internal semiconductor manufacture rather than the company’s supply to external clients.
Decrease in yield means that only a certain percentage (reported to be 10-20%) of the chip dies cut from a wafer can pass through quality control. The company’s in-house Gate-all-around (GAA) transistor architecture is believed to be the cause of this low yield. However, in terms of performance and power efficiency, the Samsung Electronics 3nm technology outperformed the previous process by a significant margin.
According to IC Nolage, Samsung Electronics’ 3-nanometer process has an integration improvement of 1.35 times, a performance improvement of 35 percent when using the same power, and a power reduction of 50 percent when using the same power. It is determined that the outcomes of the hurried implementation of the GAA procedure result in performance improvement.
TSMC, Samsung’s main competitor, is still using its existing FinFET technology for 3nm microprocessing, although manufacturing has been delayed until the end of the year due to yield concerns. After all, Apple, TSMC’s largest customer, is expected to be the first to use 3nm technology in iPhone CPUs in the 2023 model.